Verilog HDL programs for engineers in Lab | VLSI Lab programs | Xilinx Programs

                       Verilog HDL programs 

In this article, I am posting nearly 8 programs for engineers. This code is exactly working at Xilinx platform.

These all below programs are basic programs for engineers used in VLSI  lab.

1) jk flipflop xilinx code:

 
module jkflipflop(
    input j,
    input k,
    input clk,
    output reg q,
    output reg q1
    );
initial begin q = 1'b0; q1 = 1'b1;end
always@(posedge clk)
begin
case({j,k})
{1'b0,1'b0} : begin q = q; q1=q1; end
{1'b0,1'b1} : begin q = 1'b0; q1 = 1'b1; end
{1'b1,1'b0} : begin q = 1'b1; q1 = 1'b0; end
{1'b1,1'b1} : begin q = ~q;q1 = ~q1;end
endcase
end
endmodule

2) 8 to 3 priority encoder  code:

module priorityencoder(
    input [7:0]x,
    input en,
    output reg [2:0]y
    );
always@(x,en)
begin if(en == 1'b0)
casex(x)
8'b00000001 : y = 3'b000;
8'b0000001x : y = 3'b001;
8'b000001xx : y = 3'b010;
8'b00001xxx : y = 3'b011;
8'b0001xxxx : y = 3'b100;
8'b001xxxxx : y = 3'b101;
8'b01xxxxxx : y = 3'b110;
8'b1xxxxxxx : y = 3'b111;
default : y = 3'bxxx;
endcase
end
endmodule

3) BCD to 7 segments code:

module bcdtoseven(
    input [3:0]a,
    output reg [6:0]c
    );
always@(a)
begin
case(a)
0:c = 7'b1111110;
1:c = 7'b0110000;
2:c = 7'b1101101;
3:c = 7'b1101101;
4:c = 7'b0010011;
5:c = 7'b1011011;
6:c = 7'b1011111;
7:c = 7'b1110000;
8:c = 7'b1111111;
9:c = 7'b1111011;
default:c = 7'bxxx;
endcase
end
endmodule

4) 4-bit comparator code:

module magnitudecomparator(
    input [3:0]a,
    input [3:0]b,
    output reg equal,
    output reg greater,
    output reg lower
    );
always@(a or b)
begin
if(a<b)
begin
equal = 0;
lower = 1;
greater = 0;
end
else if(a==b)
begin
equal = 0;
lower = 1;
greater = 0;
end
else
begin
equal = 0;
lower = 0;
greater = 1;
end
end
endmodule

5) 16-bit arithmetic logical operator code:

module alu(
    input [15:0]a,
    input [15:0]b,
    output reg [31:0]c,
    input [3:0]x
    );
always@(a or b or x)
begin
case(x)
0:c=a+b;
1:c=a-b;
2:c=a*b;
3:c=a/b;
4:c=a%b;
5:c=a|b;
6:c=a&b;
7:c=a^b;
8:c=~a;
9:c=~b;
10:c=~(a|b);
11:c=~(a&b);
12:c=~(a^b);
13:c=a<<1;
14:c=a>>1;
default:c=a+b;
endcase
end
endmodule

6) universal shift register code:

module usr(
    input s1,
    input s0,
    input [3:0] plin,
    input lfin,
    input rtin,
    input clk,
    input reset,
    output reg q3,
    output reg q2,
    output reg q1,
    output reg q0
    );
initial begin q3=1'b0;q2=1'b0;q1=1'b0;q0 = 1'b1; end
  always@(posedge clk or posedge reset)
if(reset)
{q3,q2,q1,q0} = 4'b0000;
else
case({s1,s0})
2'b00:{q3,q2,q1,q0} = {q3,q2,q1,q0};
2'b01:{q3,q2,q1,q0} = {rtin,q3,q2,q1};
2'b10:{q3,q2,q1,q0} = {q2,q1,q0,lfin};
2'b11:{q3,q2,q1,q0} = plin;
endcase
endmodule

7) fifo(first in fifo out) code:  

module fifo(
    input[3:0] fifo_i,
    input clk,
    input clr,
    input rd,
    input wr,
    output reg [3:0] fifo_o,
    output full,
    output empty
    );
reg[2:0]ptr_diff;
reg[1:0]rd_ptr,wr_ptr;
reg[3:0]fifo[3:0];
always@(posedge clk)
begin
if(clr)
begin
rd_ptr<=2'b00;
wr_ptr<=2'b00;
ptr_diff<=3'b00;
end
else if((wr==1'b1)&&(full==1'b0))
begin
fifo[wr_ptr]=fifo_i;
wr_ptr <= wr_ptr+2'b01;
ptr_diff <= ptr_diff + 3'b001;
end
else if((rd==1'b1)&&(empty == 1'b0))
begin
fifo_o <= fifo[rd_ptr];
rd_ptr <= rd_ptr + 4'b0001;
ptr_diff <= ptr_diff - 3'b001;
end
end
assign empty = (ptr_diff == 3'b000) ? 1'b1:1'b0;
assign full = (ptr_diff == 3'b100) ? 1'b1:1'b0;
endmodule

8) modulus counter code:

module updown(
    input clk,
    input updown,
    input reset,
    output reg [3:0] cou_out
    );
initial begin cou_out = 4'b0000; end
always@(posedge clk)
begin
if(reset == 1)
cou_out <= 4'b0000;
else if(updown == 1)
begin
if(cou_out <= 4'b1001)
cou_out = cou_out + 4'b0001;
else
cou_out <= 4'b000;
end
else if(updown == 0)
begin
if(cou_out> 4'b0000)
cou_out = cou_out-4'b0001;
else
cou_out = 4'b1001;
end
end
endmodule